PapersFlow Research Brief
VLSI and Analog Circuit Testing
Research Guide
What is VLSI and Analog Circuit Testing?
VLSI and Analog Circuit Testing is the cluster of techniques for verifying Very Large Scale Integration (VLSI) circuits, including test data compression, embedded cores testing, scan testing, analog circuit fault diagnosis, BIST schemes, test access architectures, low-power testing, and delay fault testing.
The field encompasses 55,514 works focused on testing VLSI circuits and analog components. Key methods address challenges in test generation, fault modeling, simulation, and fault simulation for digital systems. Techniques also cover sequential benchmark circuits and strategies to mitigate op-amp imperfections in low-voltage CMOS technology.
Topic Hierarchy
Research Sub-Topics
Test Data Compression in VLSI Testing
This sub-topic covers encoding schemes like Huffman, FDR, and dictionary-based compression to reduce test volume and application time for scan chains in large VLSI chips. Researchers benchmark decompression hardware overhead and fault coverage.
Built-In Self-Test Schemes for VLSI Circuits
Explores BIST architectures including LFSR-based pattern generators, MISR compactors, and control logic for at-speed testing of embedded cores and memories. Studies address aliasing reduction and test time optimization.
Analog Circuit Fault Diagnosis Techniques
This area investigates signature analysis, oscillation tests, and machine learning classifiers for detecting catastrophic and parametric faults in analog blocks like op-amps and filters. Research integrates diagnosis with mixed-signal test standards.
Low-Power Testing for VLSI Circuits
Focuses on scan chain gating, multi-voltage test, and power-aware ATPG to minimize capture power and shift power during testing, preventing thermal runaway. Studies quantify power dissipation using fine-grained metrics.
Delay Fault Testing in VLSI Systems
Examines path delay fault models, launch-on-capture, and critical path selection for detecting timing defects in nanometer technologies. Researchers develop hybrid gross-small delay fault testing methodologies.
Why It Matters
VLSI and Analog Circuit Testing ensures reliability in System-on-a-Chip designs by enabling efficient fault detection in embedded cores and scan-based structures. "Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman (1994) provides coverage of test generation and fault modeling, applied in manufacturing digital ICs with 2384 citations reflecting its industry adoption. "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization" by Enz and Temes (1996) details methods like autozeroing to counter dc offset and noise in low-voltage CMOS amplifiers, critical for analog signal processing in 1815 cited applications.
Reading Guide
Where to Start
"Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman (1994) first, as it offers comprehensive coverage of test generation, fault modeling, simulation, and fault simulation for foundational understanding of digital VLSI testing.
Key Papers Explained
"Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman (1994) establishes core concepts in testable design and fault simulation (2384 citations), which "Combinational profiles of sequential benchmark circuits" by Brglez, Bryan, and Koźmiński (2003) extends with 31 benchmarks for scan-based sequential testing (2073 citations). "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization" by Enz and Temes (1996) complements by addressing analog challenges like offset in CMOS (1815 citations), linking to broader VLSI fault diagnosis.
Paper Timeline
Most-cited paper highlighted in red. Papers ordered chronologically.
Advanced Directions
Research continues on test data compression, low-power testing, and delay fault testing for System-on-a-Chip, with no recent preprints or news indicating steady focus on scaling BIST and scan techniques to advanced nodes.
Papers at a Glance
| # | Paper | Year | Venue | Citations | Open Access |
|---|---|---|---|---|---|
| 1 | Graph-Based Algorithms for Boolean Function Manipulation | 1986 | IEEE Transactions on C... | 8.8K | ✓ |
| 2 | Response Surface Methodology | 1996 | IIE Transactions | 3.8K | ✕ |
| 3 | Asymptotically Efficient Rank Invariant Test Procedures | 1972 | Journal of the Royal S... | 3.4K | ✕ |
| 4 | Modal Testing: Theory, Practice, and Application | 1998 | — | 2.7K | ✕ |
| 5 | Digital Systems Testing and Testable Design | 1994 | — | 2.4K | ✕ |
| 6 | Combinational profiles of sequential benchmark circuits | 2003 | — | 2.1K | ✕ |
| 7 | Theory and practice of error control codes | 1983 | Virtual Defense Librar... | 2.1K | ✕ |
| 8 | SIS : A System for Sequential Circuit Synthesis | 1992 | — | 1.9K | ✕ |
| 9 | Circuit techniques for reducing the effects of op-amp imperfec... | 1996 | Proceedings of the IEEE | 1.8K | ✓ |
| 10 | Resampling-Based Multiple Testing: Examples and Methods for p-... | 1994 | Biometrics | 1.7K | ✕ |
Frequently Asked Questions
What is scan testing in VLSI?
Scan testing converts sequential circuits into shift registers for test pattern application and response capture. "Combinational profiles of sequential benchmark circuits" by Brglez, Bryan, and Koźmiński (2003) presents 31 gate-level benchmarks extending ISCAS'85 for scan-based test generation research. This approach supports mixed sequential and combinational testing with 2073 citations.
How does BIST work in circuit testing?
Built-In Self-Test (BIST) schemes integrate test generation and response analysis directly into chips. "Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman (1994) discusses BIST alongside fault simulation for testable designs. These methods reduce external test equipment needs in VLSI.
What are common analog circuit fault diagnosis techniques?
Analog circuit fault diagnosis identifies defects through response analysis under test stimuli. "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization" by Enz and Temes (1996) addresses offset and noise via chopper stabilization in CMOS. Such techniques maintain dynamic range in low-gain amplifiers.
Why is test data compression used in VLSI testing?
Test data compression minimizes storage and application time for large test vector sets. The field keywords highlight test vector compression for System-on-a-Chip test efficiency. This supports low-power testing and delay fault detection in complex circuits.
What role do benchmarks play in VLSI testing research?
Benchmarks like those in "Combinational profiles of sequential benchmark circuits" by Brglez, Bryan, and Koźmiński (2003) provide standardized gate-level circuits for test generation evaluation. They extend prior sets for sequential and scan testing studies. Researchers use them to compare algorithms objectively.
How does low-power testing apply to VLSI?
Low-power testing reduces energy during test application to avoid damaging heat-sensitive chips. Field techniques include test access architectures optimized for power. This is essential for modern System-on-a-Chip with embedded cores.
Open Research Questions
- ? How can test data compression overhead be minimized while maintaining coverage for delay faults in sub-10nm VLSI?
- ? What fault models best capture analog imperfections like 1/f noise in chopper-stabilized op-amps under process variations?
- ? Which test access architectures scale efficiently for multi-core System-on-a-Chip with heterogeneous analog-digital blocks?
- ? How do scan chain reordering and low-power techniques jointly optimize test time and energy in sequential benchmarks?
- ? What BIST schemes provide at-speed testing for embedded cores without excessive area overhead?
Recent Trends
The field holds at 55,514 works with no specified 5-year growth rate.
Established papers like "Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman remain highly cited at 2384.
1994No recent preprints or news coverage in the last 12 months signals ongoing reliance on core techniques such as scan testing and analog fault diagnosis.
Research VLSI and Analog Circuit Testing with AI
PapersFlow provides specialized AI tools for Computer Science researchers. Here are the most relevant for this topic:
AI Literature Review
Automate paper discovery and synthesis across 474M+ papers
Code & Data Discovery
Find datasets, code repositories, and computational tools
Deep Research Reports
Multi-source evidence synthesis with counter-evidence
AI Academic Writing
Write research papers with AI assistance and LaTeX support
See how researchers in Computer Science & AI use PapersFlow
Field-specific workflows, example queries, and use cases.
Start Researching VLSI and Analog Circuit Testing with AI
Search 474M+ papers, run AI-powered literature reviews, and write with integrated citations — all in one workspace.
See how PapersFlow works for Computer Science researchers