Subtopic Deep Dive
Test Data Compression in VLSI Testing
Research Guide
What is Test Data Compression in VLSI Testing?
Test Data Compression in VLSI Testing uses encoding schemes like dictionary-based and Huffman methods to reduce scan chain test volume and application time in large VLSI chips.
Researchers develop techniques such as selective-entry dictionaries (Li et al., 2003, 99 citations) and fixed-length indices (Li and Chakrabarty, 2009, 81 citations) to compress test patterns for SOCs. These methods minimize ATE channel usage while maintaining fault coverage. Over 10 key papers from 1988-2014 benchmark decompression overhead against billion-gate designs.
Why It Matters
Test data compression cuts manufacturing test costs for billion-gate SoCs by reducing tester memory needs by 50-90% (Li et al., 2003). It enables testing with fewer pins, critical for high-volume production of mobile and automotive chips. Security analysis reveals vulnerabilities in compression schemes against scan attacks (Das et al., 2013), prompting secure DFT designs.
Key Research Challenges
Decompression Hardware Overhead
On-chip decompressors add area and power costs that scale poorly with test volume reduction. Li et al. (2003) report 0.5-2% area overhead for dictionary methods. Balancing compression ratio against hardware limits remains critical for sub-10nm nodes.
Fault Coverage Maintenance
Compression schemes risk dropping fault coverage due to pattern loss during encoding. Cell-aware test (Hapke et al., 2014, 185 citations) integrates transistor-level ATPG to mitigate this. Ensuring don't-care filling preserves detection rates.
Security in Compressed Scans
Test compression exposes circuits to side-channel attacks via scan chains. Das et al. (2013) analyze industrial schemes like FDR for key extraction risks. Developing secure-yet-compressible architectures addresses this dual test-security challenge.
Essential Papers
Cell-Aware Test
Friedrich Hapke, W. Redemund, Andreas Glowatz et al. · 2014 · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 185 citations
This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufacture...
Test data compression using dictionaries with selective entries and fixed-length indices
Lei Li, Krishnendu Chakrabarty, Nur A. Touba · 2003 · ACM Transactions on Design Automation of Electronic Systems · 99 citations
We present a dictionary-based test data compression approach for reducing test data volume in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed t...
Test Versus Security: Past and Present
Jean Da Rolt, A. Das, Giorgio Di Natale et al. · 2014 · IEEE Transactions on Emerging Topics in Computing · 88 citations
International audience
Test Data Compression Using Dictionaries with Fixed-Length Indices
Lei Li, Krishnendu Chakrabarty · 2009 · 81 citations
We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. Thep opl65 method is based on the use of a small number of ATE channels to deliv...
A concurrent testing technique for digital circuits
Kewal K. Saluja, Rupendra Kumar Sharma, C.R. Kime · 1988 · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 76 citations
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copyin...
X-Tolerant Test Response Compaction
Subhasish Mitra, S.S. Lumetta, Michael Mitzenmacher et al. · 2005 · IEEE Design & Test of Computers · 43 citations
Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fe...
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
Erik Jan Marinissen, Chun‐Chuan Chi, Mario Konijnenburg et al. · 2011 · Journal of Electronic Testing · 42 citations
Reading Guide
Foundational Papers
Start with Li et al. (2003, 99 citations) for dictionary basics, then Li and Chakrabarty (2009, 81 citations) for fixed-index advances; Saluja et al. (1988, 76 citations) provides concurrent testing context.
Recent Advances
Hapke et al. (2014, 185 citations) cell-aware test; Das et al. (2013, 38 citations) security; Chandra et al. (2009, 38 citations) scalable adaptive scan.
Core Methods
Dictionary encoding with ATE channels (Li et al., 2003); X-tolerant compaction (Mitra et al., 2005); selective entries and fixed indices for SOCs (Li and Chakrabarty, 2009).
How PapersFlow Helps You Research Test Data Compression in VLSI Testing
Discover & Search
Research Agent uses searchPapers('test data compression dictionary VLSI') to find Li et al. (2003, 99 citations), then citationGraph reveals 50+ citing works on selective dictionaries, and findSimilarPapers uncovers Touba variants for benchmark comparisons.
Analyze & Verify
Analysis Agent applies readPaperContent on Li and Chakrabarty (2009) to extract compression ratios, verifyResponse with CoVe cross-checks claims against Hapke et al. (2014) cell-aware data, and runPythonAnalysis simulates scan chain decompression stats using NumPy for overhead verification. GRADE scores evidence strength for fault coverage claims.
Synthesize & Write
Synthesis Agent detects gaps in secure compression post-Das et al. (2013), flags contradictions between early dictionary methods and modern FinFET needs. Writing Agent uses latexEditText for DFT sections, latexSyncCitations for 20-paper bibliography, and latexCompile for IEEE-format survey; exportMermaid diagrams scan-decompressor architectures.
Use Cases
"Benchmark Python simulation of dictionary compression ratios from Li 2003 on 1M-gate scan chains"
Research Agent → searchPapers → Analysis Agent → runPythonAnalysis (NumPy/pandas on extracted test vectors) → matplotlib plot of compression vs. overhead.
"Write LaTeX survey comparing FDR vs. Huffman for VLSI test compression"
Synthesis Agent → gap detection → Writing Agent → latexEditText + latexSyncCitations (Li/Chakrabarty papers) → latexCompile → PDF with fault coverage tables.
"Find GitHub repos implementing scan compression from 2003-2014 papers"
Research Agent → paperExtractUrls (Li 2003) → Code Discovery → paperFindGithubRepo → githubRepoInspect → verified Verilog decompressors.
Automated Workflows
Deep Research workflow scans 50+ papers via searchPapers → citationGraph on Li et al. (2003) → structured report ranking compression methods by citations and ratios. DeepScan's 7-step chain analyzes Hapke (2014) cell-aware integration with compression via readPaperContent → CoVe → GRADE. Theorizer generates hypotheses for secure 3D-SIC compression from Das (2013) and Marinissen (2011).
Frequently Asked Questions
What is test data compression in VLSI testing?
It encodes scan test patterns using dictionaries or statistical codes to shrink volume sent from ATE to chip (Li et al., 2003).
What are main compression methods?
Dictionary-based with selective entries (Li et al., 2003), fixed-length indices (Li and Chakrabarty, 2009), and response compaction like X-Tolerant (Mitra et al., 2005).
What are key papers?
Li et al. (2003, 99 citations) on selective dictionaries; Hapke et al. (2014, 185 citations) cell-aware test; Das et al. (2013) security analysis.
What are open problems?
Secure compression resistant to scan attacks (Das et al., 2013); scaling decompressors for 3D-SICs (Marinissen et al., 2011); FinFET fault coverage integration (Hapke et al., 2014).
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Part of the VLSI and Analog Circuit Testing Research Guide