Subtopic Deep Dive
Delay Fault Testing in VLSI Systems
Research Guide
What is Delay Fault Testing in VLSI Systems?
Delay Fault Testing in VLSI Systems detects timing defects using path delay fault models, launch-on-capture techniques, and critical path selection to ensure timing closure in nanometer-scale circuits.
This subtopic covers gate delay faults, robust and nonrobust test generation, and at-speed scan testing for small delay defects under process variations. Key methods include timing-aware ATPG and statistical delay quality models (SDQM). Over 1,500 citations across 10 major papers document advancements since 1986.
Why It Matters
Delay fault testing screens small delay defects in high-performance VLSI, reducing field failures in processors and SoCs. Lin et al. (2006) show timing-aware ATPG improves at-speed testing quality for nanometer designs. Sato et al. (2006) apply SDQM to quantify invisible delay defects, enhancing yield in manufacturing. Pramanick and Reddy (2003) classify robust tests, directly impacting ATPG tools used by Intel and TSMC for timing closure.
Key Research Challenges
Small Delay Defect Detection
Timing-unaware ATPG misses defects on long paths due to process variations. Ahmed et al. (2006) demonstrate higher escape rates for small defects without timing info. Needs hybrid gross-small delay models.
Critical Path Selection
Finding K longest testable paths per gate scales poorly in large circuits. Qiu and Walker (2004) propose efficient ATPG but computational cost remains high for billion-gate designs. Balancing coverage and runtime is critical.
At-Speed Test Optimization
Multi-clock domain ATPG struggles with PLL synchronization for high-frequency testing. Lin et al. (2003) optimize stuck-at and delay vectors but bridging defects require multiple-detect patterns per Benware et al. (2004).
Essential Papers
Digital logic testing and simulation
· 1986 · Microprocessors and Microsystems · 189 citations
Cell-Aware Test
Friedrich Hapke, W. Redemund, Andreas Glowatz et al. · 2014 · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 185 citations
This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufacture...
On the detection of delay faults
A.K. Pramanick, S.M. Reddy · 2003 · 167 citations
The class of faults known as gate delay faults are investigated. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to detect ga...
Impact of multiple-detect test patterns on product quality
Brady Benware, Chris Schuermyer, N. Tamarapalli et al. · 2004 · 158 citations
Abstract This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the co...
High-frequency, at-speed scan testing
Xijiiang Lin, Ron Press, Janusz Rajski et al. · 2003 · IEEE Design & Test of Computers · 155 citations
The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combin...
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
Xijiang Lin, Kun-Han Tsai, Chen Wang et al. · 2006 · Proceedings - Asian Test Symposium/Proceedings · 131 citations
In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard d...
An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit
Wangqi Qiu, D.M.H. Walker · 2004 · 120 citations
Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) meth...
Reading Guide
Foundational Papers
Start with Pramanick and Reddy (2003) for robust/nonrobust test taxonomy (167 citations), then Lin et al. (2003) for at-speed scan strategies (155 citations) to build delay testing foundations.
Recent Advances
Study Lin et al. (2006) timing-aware ATPG (131 citations) and Sato et al. (2006) SDQM (119 citations) for small defect quality metrics; Hapke et al. (2014) extends to cell-aware (185 citations).
Core Methods
Core techniques: path delay fault simulation, K-longest testable paths ATPG (Qiu and Walker, 2004), multiple-detect patterns (Benware et al., 2004), and statistical models like SDQM.
How PapersFlow Helps You Research Delay Fault Testing in VLSI Systems
Discover & Search
Research Agent uses searchPapers('delay fault testing VLSI path delay') to retrieve Pramanick and Reddy (2003) foundational work, then citationGraph reveals 167 citing papers on robust tests. findSimilarPapers on Lin et al. (2006) uncovers timing-aware ATPG variants, while exaSearch scans 250M+ papers for launch-on-capture advances.
Analyze & Verify
Analysis Agent runs readPaperContent on Sato et al. (2006) SDQM paper, then verifyResponse (CoVe) cross-checks claims against Ahmed et al. (2006) data. runPythonAnalysis simulates delay fault coverage with NumPy on K longest paths from Qiu and Walker (2004), graded by GRADE for statistical validity.
Synthesize & Write
Synthesis Agent detects gaps in small delay testing between Lin et al. (2006) and Hapke et al. (2014) cell-aware methods, flagging contradictions. Writing Agent applies latexEditText to draft ATPG methodology sections, latexSyncCitations for 10 key papers, and latexCompile for IEEE-format reports with exportMermaid timing path diagrams.
Use Cases
"Simulate coverage of K longest paths algorithm from Qiu and Walker 2004 on ITC'99 benchmarks"
Research Agent → searchPapers → Analysis Agent → runPythonAnalysis (NumPy/pandas ATPG simulation) → matplotlib delay coverage plot exported as CSV.
"Write LaTeX section comparing robust vs nonrobust delay tests from Pramanick Reddy 2003"
Research Agent → readPaperContent → Synthesis Agent → gap detection → Writing Agent → latexEditText + latexSyncCitations + latexCompile → IEEE-formatted PDF with citations.
"Find GitHub repos implementing timing-aware ATPG from Lin et al 2006 papers"
Research Agent → paperExtractUrls → Code Discovery → paperFindGithubRepo → githubRepoInspect → verified Verilog ATPG code with testbenches.
Automated Workflows
Deep Research workflow conducts systematic review: searchPapers(50+ delay fault papers) → citationGraph clustering → DeepScan 7-step analysis with CoVe checkpoints on SDQM models. Theorizer generates hybrid test hypotheses from Lin et al. (2006) and Hapke et al. (2014), validated via runPythonAnalysis simulations.
Frequently Asked Questions
What is delay fault testing?
Delay fault testing targets timing defects using gate delay and path delay models to detect slow-to-rise/fall transitions in VLSI circuits (Pramanick and Reddy, 2003).
What are main methods in delay fault testing?
Methods include robust/nonrobust path delay tests, launch-on-capture at-speed scan, and timing-aware ATPG integrating SDF files (Lin et al., 2006).
What are key papers?
Pramanick and Reddy (2003, 167 citations) classify delay tests; Lin et al. (2006, 131 citations) introduce timing-aware ATPG; Sato et al. (2006, 119 citations) define SDQM.
What are open problems?
Challenges persist in scalable K-longest path selection under variations (Qiu and Walker, 2004) and small delay defect screening in FinFETs beyond cell-aware tests (Hapke et al., 2014).
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Part of the VLSI and Analog Circuit Testing Research Guide