Subtopic Deep Dive
Low-Power Testing for VLSI Circuits
Research Guide
What is Low-Power Testing for VLSI Circuits?
Low-Power Testing for VLSI Circuits develops techniques like scan chain gating, multi-voltage test, and power-aware ATPG to minimize capture and shift power dissipation during testing, preventing thermal runaway in ICs.
This subtopic addresses excessive power consumption in scan-based testing of VLSI circuits, which can cause heat damage during manufacturing. Key methods include LFSR reseeding (Lee and Touba, 2007, 101 citations), low-transition LFSR (Nourani et al., 2008, 77 citations), and weighted pseudorandom pattern generation (Xiang et al., 2016, 72 citations). Over 10 papers from the list quantify power reduction using fine-grained metrics.
Why It Matters
Low-power testing protects VLSI devices from thermal-induced damage in high-volume manufacturing, enabling reliable test flows for complex SoCs. LFSR-reseeding by Lee and Touba (2007) reduces test power dissipation while maintaining compression, applied in BIST for mobile and embedded systems. Bit-swapping LFSR by Abu-Issa and Quigley (2009, 64 citations) cuts peak power in scan chains, critical for automotive ICs under power constraints (Chakrabarty, 2000). These techniques lower test costs and improve yield in FinFET-era designs (Hapke et al., 2014).
Key Research Challenges
Reducing Peak Capture Power
Scan testing causes high simultaneous switching in capture cycles, risking thermal runaway. Techniques like low-transition LFSR (Nourani et al., 2008) reduce transitions but struggle with fault coverage. Balancing power and coverage remains difficult in large designs.
Scan Chain Power Dissipation
Shift power in scan chains dominates test energy, addressed by reseeding (Lee and Touba, 2007). Random fill of don't-cares increases switching activity. Weighted patterns (Xiang et al., 2016) help but add reseeding overhead.
BIST Power Optimization
Built-in self-test requires low-power PRPG without external control. Bit-swapping LFSR (Abu-Issa and Quigley, 2009) lowers average power but needs scan reordering. Multi-voltage testing under place-and-route constraints complicates implementation (Chakrabarty, 2000).
Essential Papers
Cell-Aware Test
Friedrich Hapke, W. Redemund, Andreas Glowatz et al. · 2014 · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 185 citations
This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufacture...
A reconfigurable arithmetic array for multimedia applications
Alan Marshall, Tony Stansfield, Igor Kostarnov et al. · 1999 · 166 citations
In this paper we describe a reconfigurable architecture optimised for media processing, and based on 4-bit ALUs and interconnect.
Recent developments in high-level synthesis
Youn-Long Lin · 1997 · ACM Transactions on Design Automation of Electronic Systems · 115 citations
We survey recent developments in high level synthesis technology for VLSI design. The need for higher-level design automation tools are discussed first. We then describe some basic techniques for v...
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Krishnendu Chakrabarty · 2000 · 107 citations
Test access is a difficult problem encountered in the testing of core-based system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip inputs and outputs, s...
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
Jinkyu Lee, Nur A. Touba · 2007 · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 101 citations
This paper presents a new low-power test-data-compression scheme based on linear feedback shift register (LFSR) reseeding. A drawback of compression schemes based on LFSR reseeding is that the unsp...
Test Versus Security: Past and Present
Jean Da Rolt, A. Das, Giorgio Di Natale et al. · 2014 · IEEE Transactions on Emerging Topics in Computing · 88 citations
International audience
Low-Transition Test Pattern Generation for BIST-Based Applications
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed · 2008 · IEEE Transactions on Computers · 77 citations
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during test by reducing th...
Reading Guide
Foundational Papers
Start with Lee and Touba (2007) for LFSR reseeding basics (101 citations), then Nourani et al. (2008) for low-transition patterns, Chakrabarty (2000) for SoC power constraints.
Recent Advances
Xiang et al. (2016) weighted PRPG BIST; Hapke et al. (2014) cell-aware test extending to low-power FinFET flows.
Core Methods
Scan chain reordering, weighted pseudorandom generation, LFSR reseeding, bit-swapping for transition minimization.
How PapersFlow Helps You Research Low-Power Testing for VLSI Circuits
Discover & Search
Research Agent uses searchPapers('low-power scan testing VLSI') to find Lee and Touba (2007) LFSR-reseeding paper, then citationGraph reveals 101 citing works on power-aware ATPG. findSimilarPapers on Xiang et al. (2016) uncovers weighted PRPG variants; exaSearch drills into 'scan chain gating FinFET'.
Analyze & Verify
Analysis Agent applies readPaperContent to extract power metrics from Nourani et al. (2008), then runPythonAnalysis simulates LFSR transition counts with NumPy for verification. verifyResponse (CoVe) cross-checks claims against Hapke et al. (2014) cell-aware data; GRADE assigns A-grade to validated power reduction evidence.
Synthesize & Write
Synthesis Agent detects gaps in multi-voltage testing post-Chakrabarty (2000), flags contradictions between reseeding overheads. Writing Agent uses latexEditText for power waveform figures, latexSyncCitations integrates 10 papers, latexCompile generates IEEE-formatted review; exportMermaid diagrams scan chain gating flows.
Use Cases
"Compare LFSR reseeding power savings in ITC'99 benchmarks"
Research Agent → searchPapers → runPythonAnalysis (pandas on extracted tables from Lee/Touba 2007 + Nourani 2008) → matplotlib power plots → GRADE-verified comparison CSV.
"Draft low-power BIST section for VLSI test paper with citations"
Synthesis → gap detection on Xiang 2016 → Writing Agent → latexGenerateFigure (transition histograms) → latexSyncCitations (10 papers) → latexCompile → PDF with power-aware ATPG LaTeX.
"Find open-source code for bit-swapping LFSR implementation"
Research Agent → citationGraph (Abu-Issa 2009) → paperExtractUrls → paperFindGithubRepo → githubRepoInspect → verified Verilog for scan BIST power reduction.
Automated Workflows
Deep Research workflow scans 50+ low-power testing papers via searchPapers, structures report with power metrics tables from Lee/Touba (2007) and Xiang (2016). DeepScan's 7-step chain verifies LFSR claims: readPaperContent → runPythonAnalysis → CoVe → GRADE. Theorizer generates hypotheses on FinFET scan gating from Hapke (2014) + Nourani (2008) patterns.
Frequently Asked Questions
What defines low-power testing in VLSI?
Techniques minimizing shift/capture power via scan gating, LFSR reseeding (Lee and Touba, 2007), and weighted ATPG (Xiang et al., 2016) to avoid thermal damage.
What are main methods?
Low-transition LFSR (Nourani et al., 2008), bit-swapping LFSR (Abu-Issa and Quigley, 2009), reseeding for don't-care filling (Lee and Touba, 2007).
What are key papers?
Lee and Touba (2007, 101 citations) on LFSR reseeding; Nourani et al. (2008, 77 citations) on LT-LFSR; Xiang et al. (2016, 72 citations) on weighted BIST.
What open problems exist?
Power-constrained test access for SoCs (Chakrabarty, 2000); scaling reseeding to FinFETs without coverage loss; multi-voltage ATPG under routing limits.
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Part of the VLSI and Analog Circuit Testing Research Guide