PapersFlow Research Brief
Interconnection Networks and Systems
Research Guide
What is Interconnection Networks and Systems?
Interconnection Networks and Systems is the field focused on the design, architecture, and optimization of Networks on Chip (NoC) within System-on-Chip (SoC) designs, encompassing routing algorithms, performance evaluation, power optimization, wireless interconnects, fault tolerance, and multi-core processors.
This field addresses interconnection networks central to multi-core processors and SoC architectures, with 69,895 works published. Key areas include NoC architecture, routing algorithms, and power optimization. Benchmarks like SPLASH-2 and PARSEC evaluate performance in shared-memory multiprocessors.
Topic Hierarchy
Research Sub-Topics
Networks on Chip Routing Algorithms
This sub-topic examines deterministic, adaptive, and fault-tolerant routing protocols for efficient packet delivery in NoC architectures. Researchers develop and evaluate algorithms to minimize latency, maximize throughput, and ensure deadlock-freedom under varying traffic patterns.
NoC Topology Design
This sub-topic focuses on mesh, torus, fat-tree, and custom topologies tailored for specific SoC workloads. Researchers analyze trade-offs in scalability, diameter, bisection bandwidth, and implementation costs.
Power Optimization in NoCs
This sub-topic investigates dynamic voltage scaling, router sleep modes, and low-swing signaling to reduce energy consumption in NoC interconnects. Researchers model power-latency trade-offs and propose runtime adaptation techniques.
Fault Tolerance in Interconnection Networks
This sub-topic covers error-correcting codes, rerouting strategies, and graceful degradation mechanisms for reliable NoC operation under transient and permanent faults. Researchers simulate fault injection and quantify reliability metrics.
Wireless Networks on Chip
This sub-topic explores millimeter-wave wireless channels, hybrid wired-wireless architectures, and mmWave router designs to overcome wire delay limitations in 3D ICs. Researchers address interference mitigation and energy efficiency in wireless NoCs.
Why It Matters
Interconnection networks enable efficient communication in multi-core processors and SoCs used in telecommunications, multimedia, and consumer electronics. "Networks on chips: a new SoC paradigm" by Benini and De Micheli (2002) describes NoCs as solutions to time-to-market pressures in these domains, supporting complex electronic engines. Benchmarks such as "The SPLASH-2 programs" by Woo et al. (1995) and "The PARSEC benchmark suite" by Bienia et al. (2008) quantify properties like data sharing and locality in parallel applications, aiding optimization for real systems. "Principles and Practices of Interconnection Networks" by Dally and Towles (2004) addresses communication challenges in digital systems with economical network solutions pervasive across components.
Reading Guide
Where to Start
"Networks on chips: a new SoC paradigm" by Benini and De Micheli (2002), as it introduces NoC as a core paradigm for SoC communication challenges in practical domains.
Key Papers Explained
"Networks on chips: a new SoC paradigm" by Benini and De Micheli (2002) establishes NoC foundations, which "Principles and Practices of Interconnection Networks" by Dally and Towles (2004) expands with design principles for digital systems. Benchmarks in "The SPLASH-2 programs" by Woo et al. (1995) and "The PARSEC benchmark suite" by Bienia et al. (2008) build evaluation frameworks on these architectures. Graph methods from "A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs" by Karypis and Kumar (1998) support topology optimization across them.
Paper Timeline
Most-cited paper highlighted in red. Papers ordered chronologically.
Advanced Directions
Current work builds on NoC power optimization and fault tolerance, extending Dally and Towles (2004) principles to multi-core processors amid 69,895 papers. Benchmarks like PARSEC (Benia et al., 2008) guide CMP studies, with open questions in dynamic routing and wireless interconnects.
Papers at a Glance
| # | Paper | Year | Venue | Citations | Open Access |
|---|---|---|---|---|---|
| 1 | A Fast and High Quality Multilevel Scheme for Partitioning Irr... | 1998 | SIAM Journal on Scient... | 5.6K | ✕ |
| 2 | Shortest Connection Networks And Some Generalizations | 1957 | Bell System Technical ... | 4.5K | ✕ |
| 3 | On power-law relationships of the Internet topology | 1999 | — | 4.2K | ✓ |
| 4 | Validity of the single processor approach to achieving large s... | 1967 | — | 4.2K | ✕ |
| 5 | A generalized processor sharing approach to flow control in in... | 1993 | IEEE/ACM Transactions ... | 3.7K | ✕ |
| 6 | Networks on chips: a new SoC paradigm | 2002 | Computer | 3.7K | ✓ |
| 7 | A bridging model for parallel computation | 1990 | Communications of the ACM | 3.7K | ✓ |
| 8 | The SPLASH-2 programs | 1995 | — | 3.6K | ✓ |
| 9 | The PARSEC benchmark suite | 2008 | — | 3.4K | ✕ |
| 10 | Principles and Practices of Interconnection Networks | 2004 | — | 3.3K | ✕ |
Frequently Asked Questions
What are Networks on Chip in interconnection networks?
Networks on Chip (NoC) provide an integrated communication solution for System-on-Chip (SoC) designs in telecommunications, multimedia, and consumer electronics. "Networks on chips: a new SoC paradigm" by Benini and De Micheli (2002) explains that NoCs address design challenges under time-to-market constraints. They enable complex electronic engines through optimized on-chip interconnects.
How do graph partitioning algorithms apply to interconnection networks?
Graph partitioning reduces graph size by collapsing vertices and edges, partitions the smaller graph, and uncoarsens to optimize irregular graphs. "A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs" by Karypis and Kumar (1998) presents a multilevel scheme for this process. It supports efficient routing and topology design in NoC architectures.
What role do benchmarks play in evaluating interconnection networks?
"The SPLASH-2 programs" by Woo et al. (1995) characterize parallel applications for shared-address-space multiprocessors, measuring data sharing and locality. "The PARSEC benchmark suite" by Bienia et al. (2008) targets Chip-Multiprocessors (CMPs) with diverse workloads beyond high-performance computing. These suites facilitate performance evaluation of NoC designs.
What are key principles of interconnection networks?
Interconnection networks optimize communication between digital system components economically. "Principles and Practices of Interconnection Networks" by Dally and Towles (2004) covers design challenges and solutions pervasive in modern systems. They address the communication crisis in multi-core and SoC environments.
How does generalized processor sharing apply to network flow control?
Generalized processor sharing (GPS) allocates resources in rate-based flow control for integrated services networks. "A generalized processor sharing approach to flow control in integrated services networks: the single-node case" by Parekh and Gallager (1993) shows GPS provides fair service in virtual circuit packet networks. It models single-node behavior for broader network optimization.
What is the significance of shortest connection networks?
Shortest connection networks interconnect terminals with minimal direct links. "Shortest Connection Networks And Some Generalizations" by Prim (1957) provides graphical and computational procedures for solutions. These methods extend to multi-terminal generalizations relevant to NoC topologies.
Open Research Questions
- ? How can multilevel graph partitioning be adapted for dynamic NoC topologies in multi-core processors?
- ? What power optimization techniques best balance latency and energy in wireless interconnects for SoCs?
- ? How do fault-tolerant routing algorithms maintain performance under varying failure rates in large-scale NoCs?
- ? Which bridging models extend Valiant's parallel computation framework to modern CMP interconnection networks?
- ? How do power-law topologies from Internet studies inform scalable NoC architectures for exascale systems?
Recent Trends
The field encompasses 69,895 works on NoC design, routing algorithms, and power optimization, with no growth rate specified over 5 years.
High-citation papers like "Principles and Practices of Interconnection Networks" by Dally and Towles (2004, 3291 citations) remain central, alongside benchmarks such as PARSEC by Bienia et al. (2008, 3396 citations).
No recent preprints or news in the last 12 months indicate steady reliance on established architectures.
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