Subtopic Deep Dive
Strained-Silicon Technology
Research Guide
What is Strained-Silicon Technology?
Strained-silicon technology applies epitaxial strain engineering to boost carrier mobilities in planar and FinFET MOSFETs through process-induced uniaxial stress for NMOS and PMOS performance gains.
This approach incorporates strained Si into 90-nm logic nodes, increasing n-MOSFET drive current by 10% and p-MOSFET by 25% (Thompson et al., 2004). Uniaxial strain extends CMOS scaling to 45-nm nodes using piezoresistance data (Thompson et al., 2006). Over 650 papers cite foundational strained-Si implementations (Thompson et al., 2004).
Why It Matters
Strained-silicon enables cost-effective mobility enhancement in high-volume CMOS production, sustaining Moore's Law beyond 90-nm without new materials (Thompson et al., 2004; Thompson et al., 2006). Intel deployed it in 90-nm processors for 10-25% drive current gains, reducing power at fixed performance (Thompson et al., 2004). Chu et al. (2009) detail strain's role in nanoscale MOSFETs, impacting billions of transistors in logic chips. Energy dissipation modeling by Pop (2010) links strain to efficient nanoscale transport in circuits.
Key Research Challenges
Balancing NMOS-PMOS Strain
Uniaxial strain boosts electron mobility in NMOS but requires dual stressors for PMOS holes, complicating processes (Thompson et al., 2006). Piezoresistance coefficients differ, demanding separate optimization (Thompson et al., 2006). Integration in 45-nm nodes risks strain relaxation (Chu et al., 2009).
Strain Relaxation at Scale
Epitaxial strain degrades in sub-30-nm channels due to defect formation and thermal budgets (Chu et al., 2009). High-performance logic demands stable uniaxial stress across wafers (Thompson et al., 2004). Pop (2010) notes dissipation rises with incomplete strain retention.
Process Integration Complexity
Combining strained-Si with NiSi, low-k dielectrics, and Cu interconnects adds variability in 90-nm flows (Thompson et al., 2004). Schottky-barrier MOSFETs face parasitic resistance despite strain benefits (Larson and Snyder, 2006). Taur and Ning (2021) highlight tradeoffs in modern VLSI scaling.
Essential Papers
Energy dissipation and transport in nanoscale devices
Eric Pop · 2010 · Nano Research · 1.1K citations
Understanding energy dissipation and transport in nanoscale structures is of\ngreat importance for the design of energy-efficient circuits and\nenergy-conversion systems. This is also a rich domain...
Fundamentals of Modern VLSI Devices
Yuan Taur, T.H. Ning · 2021 · Cambridge University Press eBooks · 728 citations
A thoroughly updated third edition of an classic and widely adopted text, perfect for practical transistor design and in the classroom. Covering a variety of recent developments, the internationall...
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson, M Armstrong, C. Auth et al. · 2004 · IEEE Transactions on Electron Devices · 653 citations
A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logi...
Tunnel Field-Effect Transistors: State-of-the-Art
Hao Lü, Alan Seabaugh · 2014 · IEEE Journal of the Electron Devices Society · 614 citations
Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments la...
Uniaxial-process-induced strained-Si: extending the CMOS roadmap
Scott E. Thompson, Guangyu Sun, Youn Sung Choi et al. · 2006 · IEEE Transactions on Electron Devices · 578 citations
This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete...
A Logic Nanotechnology Featuring Strained-Silicon
Scott E. Thompson, M Armstrong, C. Auth et al. · 2004 · IEEE Electron Device Letters · 510 citations
Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) dri...
Overview and status of metal S/D Schottky-barrier MOSFET technology
Jeffrey Larson, John P. Snyder · 2006 · IEEE Transactions on Electron Devices · 495 citations
In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extre...
Reading Guide
Foundational Papers
Read Thompson et al. (2004, 653 citations) first for 90-nm strained-Si integration achieving 10-25% drive gains; then Thompson et al. (2006, 578 citations) for uniaxial strain history and piezoresistance data extending CMOS roadmap.
Recent Advances
Study Taur and Ning (2021, 728 citations) for updated VLSI fundamentals including strain in modern nodes; Pop (2010, 1081 citations) for energy transport linking strain to dissipation.
Core Methods
Core techniques: epitaxial SiGe for compressive PMOS strain, tensile nitride caps for NMOS, piezoresistance modeling (Thompson et al., 2006); mobility extraction via split-CV (Chu et al., 2009).
How PapersFlow Helps You Research Strained-Silicon Technology
Discover & Search
Research Agent uses searchPapers for 'strained silicon 90nm Thompson' to retrieve Thompson et al. (2004, 653 citations), then citationGraph maps 578 citing works like Thompson et al. (2006), and findSimilarPapers expands to Chu et al. (2009) for strain mechanisms.
Analyze & Verify
Analysis Agent applies readPaperContent on Thompson et al. (2004) to extract 10-25% drive current data, verifies mobility claims via verifyResponse (CoVe) against Taur and Ning (2021), and runs PythonAnalysis to plot piezoresistance from Thompson et al. (2006) data with NumPy, graded A by GRADE for evidence strength.
Synthesize & Write
Synthesis Agent detects gaps in strain relaxation post-2009 via contradiction flagging across Pop (2010) and Chu et al. (2009); Writing Agent uses latexEditText for MOSFET diagrams, latexSyncCitations to link 5 Thompson papers, and latexCompile for IEEE-formatted review.
Use Cases
"Extract mobility enhancement data from strained silicon papers and plot vs gate length."
Research Agent → searchPapers 'strained silicon mobility' → Analysis Agent → readPaperContent (Thompson 2004/2006) → runPythonAnalysis (NumPy pandas matplotlib plots drive currents vs 90/45nm lengths) → researcher gets publication-ready figure CSV.
"Draft LaTeX section on uniaxial strain in CMOS roadmap with citations."
Synthesis Agent → gap detection (post-45nm strain) → Writing Agent → latexEditText 'uniaxial strain section' + latexSyncCitations (Thompson 2006, Chu 2009) + latexCompile → researcher gets compiled PDF with equations and 10 synced refs.
"Find open-source code simulating strained Si piezoresistance."
Research Agent → paperExtractUrls (Thompson 2006) → Code Discovery → paperFindGithubRepo → githubRepoInspect (TCAD strain sims) → researcher gets verified GitHub repo with piezoresistance models linked to paper data.
Automated Workflows
Deep Research workflow scans 50+ strained-Si papers via searchPapers → citationGraph on Thompson et al. (2004) → structured report ranking by citations (e.g., 653 for 90-nm tech). DeepScan applies 7-step CoVe to verify 10-25% gains across Thompson (2004/2006), flagging dissipation issues from Pop (2010). Theorizer generates strain optimization hypotheses from piezoresistance datasets in Chu et al. (2009).
Frequently Asked Questions
What is strained-silicon technology?
Strained-silicon technology induces epitaxial or process uniaxial strain to enhance carrier mobilities in MOSFETs, boosting NMOS electrons by 10% and PMOS holes by 25% (Thompson et al., 2004).
What methods create strain in silicon?
Uniaxial-process-induced strain uses embedded SiGe stressors for PMOS and tensile caps for NMOS, integrated in 90-45nm CMOS (Thompson et al., 2006; Chu et al., 2009).
What are key papers on strained silicon?
Thompson et al. (2004, 653 citations) introduces 90-nm strained-Si logic; Thompson et al. (2006, 578 citations) details uniaxial extension; Chu et al. (2009, 364 citations) reviews nanoscale mobility.
What open problems remain in strained silicon?
Strain stability below 30-nm, dual NMOS/PMOS optimization, and integration with FinFETs persist, as defects cause relaxation (Chu et al., 2009; Taur and Ning, 2021).
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